A video encoder/decoder architecture for consumer-use HD-DVCRs

被引：0
|
作者：
An, SJ
Oh, HC
Lee, TY
Lee, YH
Kim, JS
Lee, YS
机构：
来源：
INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS, 1997 DIGEST OF TECHNICAL PAPERS | 1997年
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中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we propose a video encoder/decoder architecture for HD-DVCRs based on the 'Specifications of Consumer-Use Digital VCRs'.[1] To reduce hardware complexity a novel QNO selection algorithm is developed. The arranging algorithm of a segment is implemented with minimal memory and most hardware is shared in the encoding/decoding process. The proposed architecture's target operating frequency is 54MHz and it will be fabricated using 3-layer metal 0.6um CMOS process technology.
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页码：54 / 55
页数：2
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