High data rate synchronizers operating at low speed

被引：0

作者：

Reis, AD ^{[1
]}

Rocha, JF ^{[1
]}

Gameiro, AS ^{[1
]}

Carvalho, JP ^{[1
]}

机构：

[1] Univ Aveiro, Inst Telecomunicacoes, Dep Elect Telecomunicacoes, P-3810 Aveiro, Portugal

来源：

ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/ICECS.2001.957414

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents a new technique which allows high baud rate with low operation speed of the synchronizer. This technique is based on parallel processing. What is done by only one clock operating at the baud rate can be done by two clocks operating only at half rate. By generalizing we propose versions of clock recover circuits operating at the ratio 1/2(n) of the data rate. Thus we get circuits transmitting at very high data rate but operating at very low frequency. The proposed circuits which are transition sensitive (digital) are compared with the traditional level sensitive (analog).

引用

页码：1127 / 1130

页数：4

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