High-Speed Low-Area-Cost VLSI Design of Polar Codes Encoder Architecture Using Radix-k Processing Engines

Polar Codes applied for next-generation MIMO systems is an emerging research topic. In this work, we propose an efficient VLSI hardware architecture of the Polar encoder using radix-k processing engines. Under TSMC 90nm CMOS technology, the 16384-point radix-2 based Polar encoder design is synthesized with 0.244mm(2) under maximum clock frequency of 2.0GHz. In the similar manner, the VLSI hardware can be extended to radix-k based design. In the chip implementation with APR results, the radix-2 based Polar encoder only occupies 0.305mm(2) and dissipates 357.8mW with maximum clock frequency of 1.61GHz, delivering total throughput of 1.61Gbps.