Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench

被引：0

作者：

Carrio, F. ^{[1
]}

Kim, H. Y. ^{[2
]}

Moreno, P. ^{[3
]}

Reed, R. ^{[3
]}

Sandrock, C. ^{[3
]}

Schettino, V. ^{[4
]}

Shalyugin, A. ^{[5
]}

Solans, C. ^{[6
]}

Souza, J. ^{[4
]}

Usai, G. ^{[2
]}

Valero, A. ^{[1
]}

机构：

[1] Univ Valencia, CSIC, Inst Fis Corpuscular, E-46980 Paterna, Spain

[2] Univ Texas Arlington, Arlington, TX 76019 USA

[3] Univ Witwatersrand, ZA-2000 Johannesburg, South Africa

[4] Univ Fed Juiz de Fora, BR-36036330 Juiz De Fora, MG, Brazil

[5] Joint Inst Nucl Res, Dubna 141980, Moscow Region, Russia

[6] CERN, CH-1211 Geneva 23, Switzerland

来源：

JOURNAL OF INSTRUMENTATION | 2014年 / 9卷

关键词：

Detector control systems (detector and experiment monitoring and slow-control systems; architecture; hardware; algorithms; databases); Data acquisition concepts; Digital electronic circuits;

D O I：

10.1088/1748-0221/9/03/C03023

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

The portable test-bench for the certification of the ATLAS tile hadronic calorimeter front-end electronics has been redesigned for the present Long Shutdown (LS1) of LHC, improving its portability and expanding its functionalities. This paper presents a new test-bench based on a Xilinx Virtex-5 FPGA that implements an embedded system using a PowerPC 440 microprocessor hard core and custom IP cores. A light Linux version runs on the PowerPC microprocessor and handles the IP cores which implement the different functionalities needed to perform the desired tests such as TTCvi emulation, G-Link decoding, ADC control and data reception.

引用

页数：12

共 50 条

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