Wafer Level Chip Scale Package Copper Pillar Probing

被引：0

作者：

Chen, Hao ^{[1
]}

Lin, Hung-Chih ^{[1
]}

Peng, Ching-Nen ^{[1
]}

Wang, Min-Jer ^{[1
]}

机构：

[1] Taiwan Semicond Mfg Co Ltd, 6,Creat Rd 2,Hsinchu Sci Pk, Hsinchu 30077, Taiwan

来源：

2014 IEEE INTERNATIONAL TEST CONFERENCE (ITC) | 2014年

关键词：

Integration fan-out wafer level chip scale package (InFO WLCSP); copper pillar; known-good-die (KGD); wafer level final test (WLFT); redistribution layer (RDL); probe card; MEMS (micro electro mechanical system); automatic testequipment (ATE); touch-down; polish; overdrive;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper introduces a probing methodology for Integrated Fan Out Wafer Level Chip Scale Packaging (InFO WLCSP) which has the promise of being a very cost effective solution to achieve "More than Moore's law" for mobile devices - more so than 3D integrated circuits (3DIC). InFO WLCSP can use either Aluminum (Al) pads or Copper (Cu) pillars as contact interfaces. Cu pillars without solder caps are selected as the contact interface due to their superior area and cost efficiency. However, there are some challenges due to Cu oxidation and its small size. In this paper we propose a novel methodology that leads to a very high precision test resulting in better yield for mass production of InFO WLCSP packages. We will show results on some industrial designs to validate our claims.

引用

页数：6

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