An Accurate Device-Level Simulation Method to Estimate Cross Sections of Single Event Upsets by Silicon Thickness in Raised Layer

被引：0

作者：

Kojima, Kentaro ^{[1
]}

Yamada, Kodai ^{[1
]}

Furuta, Jun ^{[1
]}

Kobayashi, Kazutoshi ^{[1
]}

机构：

[1] Kyoto Inst Technol, Grad Sch Sci & Technol, Kyoto, Japan

来源：

2019 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2019年

基金：

日本科学技术振兴机构;

关键词：

single event effect; soft error; heavy ion irradiation; FDSOI; flip flop; device simulation; NMOS; PMOS;

D O I：

10.1109/irps.2019.8720481

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An accurate device-level simulation method to estimate cross sections (CS) of single event upsets for a standard latch is proposed. CS from the proposed method is compared with experimental results by heavy ions on a fabricated chip in a 65 nm FDSOI. Silicon thickness below silicide is parameterized to make CS coincident between simulation and measurement results. Silicon thickness is highly correlated to soft-error tolerance. By increasing silicon thickness, simulation results becomes closer to the measurement results. Device simulation results show that the cross section is proportional to the silicon thickness in the raised layer below silicide.

引用

页数：5