Reconfigurable hardware SAT solvers: A survey of systems

被引:44
|
作者
Skliarova, I [1 ]
Ferrari, AD [1 ]
机构
[1] Univ Aveiro, Dept Elect & Telecommun, IEETA, P-3810193 Aveiro, Portugal
关键词
Boolean satisfiability; reconfigurable computing; FPGA; hardware acceleration;
D O I
10.1109/TC.2004.102
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
By adapting to computations that are not so well-supported by general-purpose processors, reconfigurable systems achieve significant increases in performance. Such computational systems use high-capacity programmable logic devices and are based on processing units customized to the requirements of a particular application. A great deal of the research effort in this area is aimed at accelerating the solution of combinatorial optimization problems. Special attention in this context was given to the Boolean satisfiability (SAT) problem resulting in a considerable number of different architectures being proposed. This paper presents the state-of-the- art in reconfigurable hardware SAT satisfiers. The analysis and classification of existing systems has been performed according to such criteria as algorithmic issues, reconfiguration modes, the execution model, the programming model, logic capacity, and performance.
引用
收藏
页码:1449 / 1461
页数:13
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