Low-power CMOS digital design with dual embedded adaptive power

被引：39

作者：

Kuroda, T ^{[1
]}

Hamada, M ^{[1
]}

机构：

[1] Toshiba Co Ltd, Mobile & Network LSI Dev Grp, Syst ULSI Engn Lab, Kawasaki, Kanagawa 2108520, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2000年 / 35卷 / 04期

关键词：

adaptive power-supply system; clustered voltage scaling; low-power CMOS design; multiple supply voltages;

D O I：

10.1109/4.839927

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low-power CMOS design methodology with dual embedded adaptive power supplies is presented, A variable supply-voltage scheme for dual power supplies, namely, the dual-VS scheme, is presented. It is found that the lower supply voltage should be set at 0.7 of the higher supply voltage to minimize chip power dissipation. This knowledge aids designers in decision of the optimal supply voltages within a restricted design time, An MEPG-4 video codec chip is designed at 2.5 and 1.75 V for internal circuits that are generated from an external power supply of 3.3 V by the dual-VS circuits, Power dissipation is reduced by 57% without degrading circuit performance compared to a conventional CMOS design.

引用

页码：652 / 655

页数：4

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