Fast hazard detection in combinational circuits

被引：0

作者：

Jeong, C ^{[1
]}

Nowick, SM ^{[1
]}

机构：

[1] Columbia Univ, Dept Comp Sci, New York, NY 10027 USA

来源：

41ST DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2004 | 2004年

关键词：

logic design; asynchronous circuits; hazards;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In designing asynchronous circuits it is critical to ensure that circuits are free of hazards in the specified set of input transitions. In this paper, two new algorithms are proposed to determine if a combinational circuit is hazard-free without exploring all its gates, thus providing more efficient hazard detection. Experimental results indicate that the best new algorithm on average visits only 20.7% of the original gates, with an average runtime speedup of 1.69 and best speedup of 2.27 (for the largest example).

引用

页码：592 / 595

页数：4

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