Novel Tri-State Latch using Single-Peak Negative Differential Resistance Devices

被引：0

作者：

Shin, Sunhae ^{[1
]}

Kim, Kyung Rok ^{[1
]}

机构：

[1] Ulsan Natl Inst Sci & Technol, Elect & Comp Engn, Ulsan, South Korea

来源：

2014 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW) | 2014年

基金：

新加坡国家研究基金会;

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We propose a novel tri-state latch based on single-peak MOS-NDR. By shifting peak voltage over half of the supply voltage, tri-state memory can be implemented. The fully suppressed valley current of MOS-NDR guarantees the supply voltage design marigin in tri-state logic and memory.

引用

页数：2

共 45 条

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