Real-time Testing of True Random Number Generators through Dynamic Reconfiguration

被引：7
|
作者：
Hotoleanu, Dan [1 ]
Cret, Octavian [1 ]
Suciu, Alin [1 ]
Gyorfi, Tamas [1 ]
Vacariu, Lucia [1 ]
机构：
[1] Tech Univ Cluj Napoca, Dept Comp Sci, Cluj Napoca, Romania
来源：
13TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS | 2010年
关键词：
Dynamic reconfiguration; TRNG; NIST test suite; FPGA;
D O I：
10.1109/DSD.2010.56
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents the hardware implementation of the widely known NIST Statistical Test Suite a battery of statistical tests for pseudorandom number generators (PRNGs) and true random number generators (TRNGs) in a single Xilinx FPGA chip, using dynamic partial reconfiguration. The design offers a basic framework for easy integration of any additional randomness evaluation tests as well. Due to the integration of both the TRNG and the tests suite in a single FPGA chip, our solution offers new opportunities in the area of random number generation and testing, greatly reducing the time between the generation and the validation of the generated sequences of random bits.
引用
收藏
页码：247 / +
页数：2
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