Closed-form Expressions for Extraction of Capacitances in Multilayer VLSI Interconnects

被引：0
|
作者：
Sharma, Rohit [1 ]
Nitin [1 ]
Sehgal, Vivek Kumar [1 ]
Chauhan, D. S. [1 ]
机构：
[1] Jaypee Univ Informat Technol, Solan 173215, HP, India
来源：
2008 IEEE REGION 10 CONFERENCE: TENCON 2008, VOLS 1-4 | 2008年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this work, we report closed-form analytical expressions for capacitances in multilayer VLSI interconnect circuits, using conventional techniques for analysis of strip-line like structures. Variational analysis combined with transverse transmission line technique is used for the determination of capacitances, and a new set of closed-form expressions are derived which gives accurate results without any inherent assumptions. The comparisons of the results with available data in the published literature, as well as 3-D simulation results, are also discussed.
引用
收藏
页码：2236 / 2239
页数：4
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