On the Analysis and the Mitigation of Power Supply Noise and Power Distribution Network Impedance Variation for Scan-Based Delay Testing Techniques

被引:3
|
作者
Thibeault, Claude [1 ]
Gagnon, Ghyslain [1 ]
机构
[1] Ecole Technol Super, Elect Engn Dept, Montreal, PQ H3C 1K3, Canada
关键词
Intermodulation distortion; power issues; power supply noise (PSN); resonance; scan-based delay testing; DROOP; SOCS;
D O I
10.1109/TVLSI.2018.2817177
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, we analyze the impact of the power supply noise and the power distribution network (PDN) impedance variation on the timing margin in both modes for ICs with multiple clock domains. We investigate the so-called intermodulation products (IMPs). We show that IMPs are mainly induced by the dependent nature of the transistors. We also provide experimental results showing that scan-based delay testing can be optimistic with respect to the mission mode for maximum achievable nominal frequency prediction, even at lower clock frequencies. We also show that IMPs can induce timing margin fluctuations that can be larger than that of the ones induced by the voltage droop in the test mode. Using an improved HSpice simulation model of a PDN validated by experimental results, we also quantify the timing margin variation due to power noise in the test mode as a function of the clock frequency, including the so-called clock stretching phenomenon. Finally, we propose a robust test signal scheme for multiple clock domain chips. The simulation results reveal that this scheme is less sensitive to PDN impedance variation than that of the most popular existing test schemes, and that it provides timing margins closer to those obtained in the mission mode.
引用
收藏
页码:1377 / 1390
页数:14
相关论文
共 50 条
  • [1] A New Delay Testing Signal Scheme Robust to Power Distribution Network Impedance Variation
    Thibeault, Claude
    Louati, Ali
    [J]. 2017 IEEE 35TH VLSI TEST SYMPOSIUM (VTS), 2017,
  • [2] Power supply noise in delay testing
    Wang, Jing
    Walker, D. M. H.
    Majhi, Ananta
    Kruseman, Bram
    Gronthoud, Guido
    Villagra, Luis Elvira
    van de Wiel, Paul
    Eichenberger, Stefan
    [J]. 2006 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, 2006, : 510 - +
  • [3] A Novel Scan Architecture for Low Power Scan-Based Testing
    Naeini, Mahshid Mojtabavi
    Ooi, Chia Yee
    [J]. VLSI DESIGN, 2015, 2015
  • [4] Scan chain design for shift power reduction in scan-based testing
    LI Jia 1
    2 The Institute of Computing Technology
    [J]. Science China(Information Sciences), 2011, 54 (04) : 767 - 777
  • [5] Modeling power supply noise in delay testing
    Wang, Jing
    Walker, Duncan M.
    Lu, Xiang
    Majhi, Ananta
    Kruseman, Bram
    Gronthoud, Guido
    Villagra, Luis Elvira
    van de Wiel, Paul J. A. M.
    Eichenberger, Stefan
    [J]. IEEE DESIGN & TEST OF COMPUTERS, 2007, 24 (03): : 226 - 234
  • [6] Scan chain design for shift power reduction in scan-based testing
    Jia Li
    Yu Hu
    XiaoWei Li
    [J]. Science China Information Sciences, 2011, 54 : 767 - 777
  • [7] Scan chain design for shift power reduction in scan-based testing
    Li Jia
    Hu Yu
    Li XiaoWei
    [J]. SCIENCE CHINA-INFORMATION SCIENCES, 2011, 54 (04) : 767 - 777
  • [8] Measurement-based analysis of delay variation induced by dynamic power supply noise
    Fukazawa, Mitsuya
    Nagata, Makoto
    [J]. IEICE TRANSACTIONS ON ELECTRONICS, 2006, E89C (11): : 1559 - 1566
  • [9] Delay variation analysis in consideration of dynamic power supply noise waveform
    Fukazawa, Mitsuya
    Nagata, Makoto
    [J]. PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2006, : 865 - 868
  • [10] On reducing both shift and capture power for scan-based testing
    Li, Jia
    Xu, Qiang
    Hu, Yu
    Li, Xiaowei
    [J]. 2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2008, : 619 - +