Multi-objective optimization of a parameterized VLIW architecture

The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to implement. Architectures based on Very Long Instruction Word (VLIW), in particular have found fertile ground in multimedia electronic appliances thanks to their ability to exploit high degrees of Instruction Level Parallelism (ILP) with a reasonable trade-off in complexity and silicon costs. In this case ASIP specialization may require not only manipulation of the instruction-set but also tuning of the architectural parameters of the processor and the memory subsystem. Setting the parameters so as to optimize certain metrics requires the use of efficient Design Space Exploration (DSE) strategies, simulation tools and accurate estimation models operating at a high level of abstraction. In this paper we present a framework for evaluation, in terms of performance, cost and power consumption, of a system based on a parameterized VLIW microprocessor together with the memory hierarchy. Further the framework implements a number of multi-objective DSE strategies to obtain Pareto-optimal configurations for the system.