Avalanche and Short-Circuit Robustness of 4600 V SiC DMOSFETs

A comprehensive investigation of the operating limits and failure modes for 4600 V/7.78 mm(2) SiC DMOSFETs under unclamped inductive switching (UIS) and short-circuit conditions is performed. Maximum single-pulse avalanche energies (E-AS) of 1.07 J (13.75 J/cm(2)) and avalanche withstand times (t(AV)) as high as 71 mu s are recorded. The variation of E-AS and t(AV) with load inductance (or avalanche current) is quantified. Stability of the key DMOSFET performance characteristics including R-DS,R- on, V-TH, body-diode, gate/drain leakage currents and terminal capacitances under both single-pulse and repetitive (up to 1000 shots) avalanche conditions are examined. Short-circuit withstand times (t(SC)) in the range of 3-14 mu s are recorded on the DMOSFETs, The impact of various factors such as the device design, gate drive voltage, DC link (drain) voltage, and operating temperature on the t(SC) is quantified. The evolution of the I-V and C-V characteristics under short-circuit operation is examined, and failure mechanisms are suggested.