Design and optimization of dynamically reconfigurable embedded systems

In this paper, we target on architecture consisting of a processor and a field programmable gate array (FPGA), where the FPGA can be reconfigured in run-time to perform different tasks. Dynamic reconfiguration provides a performance/cost advantage over load-time configuration, but a good design methodology is essential. We describe a C-based design flow, for the architecture. To address the performance concern, a concept of two-stage optimization is proposed, and various design steps are defined and applied. An MPEG-2 decoder is taken as a design example. The preliminary results show, the effectiveness of our methodology.