Limits of Synchronization Accuracy Using Hardware Support in IEEE 1588

Clock synchronization protocols for packet-oriented networks, like IEEE 1588, depend on time stamps drawn from a local clock at distinct points in time. Due to the fact that software-generated time stamps suffer from jitter caused by non-deterministic execution times, many implementations for high precision clock synchronization rely on hardware support. This allows time readings for packets with very low jitter close to the physical layer. Nevertheless, approaches using hardware support have to carefully consider influences on synchronization accuracy when it comes to the range of nanoseconds. Among others, limits come from the update interval, oscillator stability, or hardware clock frequency. This paper enlightens the limits for such implementations based on an analysis of the influences of the main factors for jitter. The conclusions give hints for efficiently optimizing current implementations.