A CMP-free Cu/low-k integration technology by Cu pillar/line and PS-low-k STP process

被引：0

作者：

Shishiguchi, S ^{[1
]}

Fukuda, T ^{[1
]}

Kochiya, H ^{[1
]}

Yanazawa, H ^{[1
]}

Matsunaga, H ^{[1
]}

机构：

[1] ASET, NTT Atsugi R&D Ctr, Atsugi, Kanagawa 2430198, Japan

来源：

ADVANCED METALLIZATION CONFERENCE 2001 (AMC 2001) | 2001年

关键词：

D O I：

暂无

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

A novel method of Cu/low-k integration is proposed and the key process results are presented. The technology does not employ CMP, and involves the formation of Cu pillars or lines followed by STP (spin coating, film transfer, and hot pressing) using a photosensitive low-k material. Cu pillars or lines for interconnects are fabricated by bottom-up Cu electroplating on a Cu seed layer masked with photoresist patterns. STP fills the gaps between the pillars or lines with a low-k dielectric (k = 2.9) and planarizes the surface at the same time. Cu/low-k integration was demonstrated for a feature size of 0.5 mum.

引用

页码：57 / 60

页数：4

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