Implicit deductive fault simulation for complex delay fault models

被引:3
|
作者
Deodhar, JV [1 ]
Tragoudas, S
机构
[1] Intel Corp, Texas Dev Ctr, Austin, TX 78746 USA
[2] So Illinois Univ, Dept Elect & Comp Engn, Carbondale, IL 62901 USA
基金
美国国家科学基金会;
关键词
delay fault testing; fault grading; fault simulation; path delay fault (PDF); segment delay fault (SDF);
D O I
10.1109/TVLSI.2004.827598
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper introduces an implicit version of the well-known deductive fault simulation technique suitable to delay fault models with an exponential number of faults. The proposed method calculates the fault coverage by generating lists of entities for each line during a single topological circuit traversal. Each stored entity only contains a number and a subset of the test vectors. No delay faults are stored, and no special data structures are required. There are significant differences between the presented implicit method and fault coverage using deductive fault simulation. The method is shown to be effective for delay the path and segment delay fault models.
引用
收藏
页码:636 / 641
页数:6
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