Digital column readout architectures for hybrid pixel detector readout chips

被引：11

作者：

Poikela, T. ^{[1
,3
]}

Plosila, J. ^{[2
]}

Westerlund, T. ^{[2
]}

Buytaert, J. ^{[3
]}

Campbell, M. ^{[3
]}

De Gaspari, M. ^{[3
]}

Llopart, X. ^{[3
]}

Wyllie, K. ^{[3
]}

Gromov, V. ^{[4
]}

Kluit, R. ^{[4
]}

van Beuzekom, M. ^{[4
]}

Zappon, F. ^{[4
]}

Zivkovic, V. ^{[4
]}

Brezina, C. ^{[5
]}

Desch, K. ^{[5
]}

Fu, Y. ^{[5
]}

Kruth, A. ^{[5
]}

机构：

[1] TUCS Turku Ctr Comp Sci, Turku 20520, Finland

[2] Univ Turku, Dept Informat Technol, FI-20014 Turun, Finland

[3] CERN, CH-1211 Geneva, Switzerland

[4] NIKHEF H, NL-1098 XG Amsterdam, Netherlands

[5] Univ Bonn, Inst Phys, D-53115 Bonn, Germany

来源：

JOURNAL OF INSTRUMENTATION | 2014年 / 9卷

关键词：

VLSI circuits; Front-end electronics for detector readout; Digital electronic circuits; LHCB VELO UPGRADE;

D O I：

10.1088/1748-0221/9/01/C01007

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

In this paper, two digital column architectures suitable for sparse readout of data from a pixel matrix in trigger-less applications are presented. Each architecture reads out a pixel matrix of 256 x 256 pixels with a pixel pitch of 55 mu m. The first architecture has been implemented in the Timepix3 chip, and this is presented together with initial measurements. Simulation results and measured data are compared. The second architecture has been designed for Velopix, a readout chip planned for the LHCb VELO upgrade. Unlike Timepix3, this has to be tolerant to radiation-induced single-event effects. Results from post-layout simulations are shown with the circuit architectures.

引用

页数：9

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