Automatic Test Bench Generation and Connection in Modern Verification Environments: Methodology and Tool

Due to complex designs and time to market pressure verification closure is the bottleneck in ASIC/SoC design. Hence setting up a constrained random testbench environment seems to be a difficult task, especially when we consider that environments need to be flexible, scalable, and reusable. Although standard verification methodologies such as UVM [1], OVM [2] or VMM [3] help to an extent, but then creating testbench environment still consumes a lot of time. This calls for the need of testbench automation. There has been a lot of development in testbench automation techniques but still the problem of connectivity between the VIP interface and DUT remains unsolved which consumes considerable amount of time at SoC level. To solve this problem a novel technique has been proposed. The aim is to achieve a correct by construction technique to get the various existing components from IP level and make the automatic connection of the verification component with the design under test.