Design and Implementation of a 118 MHz 2D DCT Processor

被引：0

作者：

Atani, Reza Ebrahimi ^{[1
]}

Baboli, Mehdi ^{[1
]}

Mirzakuchaki, Sattar ^{[1
]}

Atani, Shahabaddin Ebrahimi ^{[2
]}

Zamanlooy, Babak ^{[1
]}

机构：

[1] Iran Univ Sci & Technol, Dept Elect Engn, Tehran 16846, Iran

[2] Univ Guilan, Dept Math, Rasht, Iran

来源：

2008 IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS, VOLS 1-5 | 2008年

关键词：

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Frequency analysis using the Discrete Cosine Transforms (DCT) is an obvious choice for Digital signal and Image processing domain. This paper describes the implementation of 2D-DCT processor for the synchronous design in a Xilinx VertexIV FPGA device. The DCT core architecture is based on the distributed arithmetic. The total dynamic power of the processor is 371 mW, in an operating frequency of 118.2 MHz is achieved. The paper presents the trade-offs involved in designing the architecture, the design for performance issues and the possibilities for future development

引用

页码：2311 / +

页数：3

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