A high gain and high yield 0.14 μm Au/WSi buried gate HJFET technology with directly dry-etched SiO2 openings

被引：0

作者：

Wakejima, A ^{[1
]}

Makino, Y ^{[1
]}

Yamanoguchi, K ^{[1
]}

Onda, K ^{[1
]}

Hori, Y ^{[1
]}

Maruhashi, K ^{[1
]}

Miyamoto, H ^{[1
]}

Samoto, N ^{[1
]}

Kanamori, M ^{[1
]}

Ohata, K ^{[1
]}

机构：

[1] NEC Corp Ltd, Kansai Elect Res Labs, Otsu, Shiga 5200833, Japan

来源：

COMPOUND SEMICONDUCTORS 1998 | 1999年 / 162期

关键词：

D O I：

暂无

中图分类号：

O4 [物理学];

学科分类号：

0702 ;

摘要：

A Y-shaped 0.14 mum gate AlGaAs/InGaAs HJFET has been developed using a direct SiO2 opening technology which consists of two step dry-etching with chemically amplified resist mask. A small deviation of 1 0 nm in Lg was obtained for 0.14 mum gate on 4-inch wafers and standard deviation of Vth achieved was 55 mV. The distance between the top of the gate and the recess surface (hg) was simulated using a two-dimensional device simulator in order to investigate the relation between hg and a fringing gate to drain capacitance. As the result, the fabricated HJFET showed extremely high gain performance of 13dB MSG at 60 GHz.

引用

页码：231 / 236

页数：6