Use of superlattice thermionic emission for "hot spot" reduction in a convectively-cooled chip

The ITRS roadmap indicates the thermal solution for high performance and cost performance computers must improve by a factor of two over the next decade to keep pace with the development of electronic equipment. However, the roadmap does not address the spatially non-uniform beating issues caused by densely routed circuitry. The localized high heat fluxes that occur due to non-uniform heating require an even more aggressive thermal solution to ensure the circuit temperature stays below the specified value. An approach to mitigating the effect of localized "hot spots" is the spread some of the heat from the high heat flux areas to areas of lower heat flux on the chip and/or substrate. Heat spreading at the die level may be accomplished through high thermal conductivity coatings on the backside of the silicon and/or the use of micro heat pipes. Alternatively, solid-state-energy-conversion devices, such as those employing thermionic emission, can be bonded to the back of the silicon chip. The solid state coolers absorb heat at the localized "hot spot" region and transport it via electrons to a region of lower heat flux. Si/SiGe superlattice micro-coolers have demonstrated a cooling power density exceeding 500 W/cm(2) in an isolated configuration. In this study we investigate the integration and packaging of such micro-coolers with IC chips. Preliminary results suggest that a significant reduction in temperature can be achieved for 70 micron localized hot spots dissipating 100's of W/cm(2).