Memory-Access Optimization for Acceleration and Power Saving of FPGA-Based Image Processing

被引：0
|
作者：
Shimohane, Shungo [1 ]
Inoue, Toshiyuki [1 ]
Tsuchiya, Akira [1 ]
Kishine, Keiji [1 ]
机构：
[1] Univ Shiga Prefecture, Dept Elect Syst Engn, 2500 Hassaka, Hikone, Shiga 5228533, Japan
来源：
2022 19TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | 2022年
关键词：
D O I：
10.1109/ISOCC56007.2022.10031293
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we propose a method for acceleration and power saving of FPGA-based image processing by optimizing memory access. The BRAM-based System can improve the data-transmission speed between the FPGA and memory device by storing the image-processed data in BRAM. Also, it does not require an additional driver to absorb the latency, which leads to reducing the hardware-resource usage and the power consumption. Our memory-access optimization enables that the processing speed is increased by about 9 times and the power consumption is reduced by 10% compared to that of the conventional DRAM-based system.
引用
收藏
页码：338 / 339
页数：2
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