Impact of intrinsic parameter fluctuations on the performance of In0.75Ga0.25As implant free MOSFETs

被引:2
|
作者
Seoane, N. [1 ]
Garcia-Loureiro, A. [1 ]
Aldegunde, M. [1 ]
Kalna, K. [2 ]
Asenov, A. [2 ]
机构
[1] Univ Santiago de Compostela, Dept Elect & Comp Sci, Santiago De Compostela 15782, Spain
[2] Univ Glasgow, Dept Elect & Elect Engn, Glasgow G12 8LT, Lanark, Scotland
基金
英国工程与自然科学研究理事会;
关键词
NANO-MOSFETS; SIMULATION; CMOS; GATE;
D O I
10.1088/0268-1242/24/5/055011
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We investigate the level of statistical variability in implant free (IF) MOSFETs, which are one of the most promising candidates III-V channels implementation. We report results for the threshold voltage (V-T) fluctuations in aggressively scaled IF III-V MOSFETs induced by random discrete dopants in the delta-doping plane obtained using 3D drift-diffusion (D-D) device simulations. The D-D simulator is meticulously calibrated against results obtained from ensemble Monte Carlo device simulations. The simulated 30, 20 and 15 nm gate length In0.75Ga0.25As channel IF transistors exhibit threshold voltage standard deviations of 42, 58 and 61 mV, respectively, at a drain voltage of 0.1 V. At a drain voltage of 0.8 V, the threshold voltage standard deviations increase to 55, 71 and 81 mV, respectively. While the standard deviations of V-T in the 30 and 20 nm IF MOSFETs are close to those observed in bulk Si MOSFETs with equivalent gate lengths, the threshold voltage standard deviation in the 15 nm gate length IF MOSFET is lower.
引用
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页数:7
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