A 16.1-b ENOB 0.064mm2 Compact Highly-Digital Closed-Loop Single-VCO-based 1-1 SMASH Resistance-to-Digital Converter in 180nm CMOS

This paper presents a novel highly-digital area and energy-efficient closed-loop time-based CMOS single-ended resistive sensor-to-digital readout circuit. It achieves a high resolution of 16.1 hits utilizing a time-based implementation in an extremely small area of only 0.064mm(2). It employs a single VCO and a digital feedback loop for the read-out of an external single-ended resistive sensor such as a NTC thermistor. In addition to inherent 1st-order quantization noise shaping due to the oscillator, a second loop in SMASH configuration creates 2nd-order noise shaping. The fabricated prototype in a 180nm CMOS process achieves 16.1 bit of resolution for 1ms conversion time and consumes 171 mu W, resulting in a 2.4pJ/c.s. FOMw, which is excellent for a resistive sensor interface. Thanks to the closed loop architecture, it also achieves more than 13 bits of linearity.