Tunnel-FET Inverters for Ultra-low Power Logic with Supply Voltage down to VDD=0.2 V

被引：0
|
作者：
Richter, S. [1 ]
Trellenkamp, S. [1 ]
Schaefer, A. [1 ]
Hartmann, J. M. [2 ]
Bourdelle, K. K. [3 ]
Zhao, Q. T. [1 ]
Mantl, S. [1 ]
机构：
[1] Forschungszentrum Julich, JARA FIT, Peter Grunberg Inst PGI IT 9, D-52425 Julich, Germany
[2] CEA LETI, F-38054 Grenoble, France
[3] SOITEC, Parc Technolog Fontaines, F-38190 Bernin, France
来源：
2014 15TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (ULIS) | 2014年
关键词：
TFET; inverter; SiGe; heterostructure; nanowire; TRANSISTORS;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Complementary MOSFET and Tunnel-FET inverters based on tri-gated strained Si nanowire arrays are demonstrated. The voltage transfer characteristics as well as the inverter supply currents of both inverter types are analyzed and compared. A degradation of the inverter output voltage is observed due to the ambipolar TFET characteristics. Emulated TFET inverters based on the measured transfer characteristics of SiGe/Si heterostructure nanowire array n-channel TFETs with reduced ambipolarity demonstrate inverter switching for supply voltages down to V-DD = 0.2 V.
引用
收藏
页码：13 / 16
页数：4
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