A high speed Sorting Processor ASIC for the RPC Trigger System of the CMS experiment

被引：0
|
作者：
De Robertis, G [1 ]
Loddo, F [1 ]
Ranieri, A [1 ]
机构：
[1] Ist Nazl Fis Nucl, Sezione Bari, I-70125 Bari, Italy
来源：
NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT | 1999年 / 436卷 / 03期
关键词：
D O I：
10.1016/S0168-9002(99)00470-2
中图分类号：
TH7 [仪器、仪表];
学科分类号：
0804 ; 080401 ; 081102 ;
摘要：
The design of a high speed Sorting Processor ASIC is presented. It was designed in BiCMOS 0.8 mu m technology and its aim is to reorder and provide the four highest words among eight input words, in decreasing order. This chip is the main component of the sorting tree of the Trigger Muon System of the CMS experiment. (C) 1999 Elsevier Science B.V. Ail rights reserved.
引用
收藏
页码：394 / 400
页数：7
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