A High-Throughput Low-Complexity VLSI Architecture for ZF Precoding in Massive MIMO

In this work we present a high-throughput, low complexity design for linear precoding in massive Multiple Input Multiple-Output (MIMO) systems. Large number of Base Station (BS) antennas in massive MIMO at one hand has caused the performance of linear precoders to be near-optimal and at the other hand has increased their complexity due to the need for the inversion of matrices with large dimensions. To avoid this complexity, approximate inversion methods based on Neumann Series have been proposed. However, in this work, we propose an architecture for Zero Forcing (ZF) precoder based on the Neumann Series approximate inversion that further reduces the complexity by replacing matrix-matrix multiplications with matrix-vector multiplications. The proposed method is motivated by the fact that the final output of a precoder is a vector of precoded data not the precoding matrix itself. Finally we present the implementation results on a Xilinx Virtex-7 XC7VX485T and also Kintex-7 410T FPGAs and compare the achieved results with similar designs. These results show that our architecture achieves higher throughput with a lower complexity providing the same accuracy compared to the reported designs to-date.