A Machine Learning Based Wafer Test Ranking for Root Cause Analysis

The verification process represents a major challenge in the integrated circuits industry due to the ever-increasing complexity of modern analog integrated circuits. This is why the need to develop the most effective methods for identifying source faults has become a necessity in order to ensure exceptional quality at a reasonable cost. In the post-silicon verification process, the wafers are thoroughly tested and faulty behaviors are inevitably detected. The process of determining the cause of the faulty behavior is referred to as root cause analysis. The root cause analysis for wafer tests may involve the signal analysis of certain test sensors outputs that usually is performed visually by the test engineers in order to establish the root cause associated to faulty wafers. This implies the ranking assessment of the visual degree of correlation between each sensor outputs and pass/fail wafer labels of a produced set of wafers. Based on this ranking it is possible to identify which technological process steps were causing the majority of defect wafers. This is a time and resource consuming process due to the high number of performed tests and produced wafers that need to be visually inspected. This paper addresses the automation of this type of root cause analysis of wafer defects by making use of signal analysis metrics based Dynamic Time Warping (DTW) combined with Support Vector Machine (SVM) classifier or Davies-Bouldin metric. The proposed method's quality was evaluated on a set of 971 labeled wafers and their corresponding 56 ranked test signals, providing similar conclusions as the visually ranking method performed by the test engineers.