CMOS Large-Signal Substrate Modeling for High-Power RF Switch Design

An improved CMOS large-signal model including the substrate/triple-well characteristics has been proposed for the application in high power-handling of CMOS RF switch circuit. In order to establish a NMOS transistor model in RF switch application, two types of test devices, series-and shunt-type NMOS transistors, have been designed and fabricated by using a standard CMOS 0.18 mu m technology. Based on the measured results of insertion loss and power-handling capability, the substrate parasitic RC and pn-well junction diodes were embedded into a conventional BSIM3 model for characterizing RF small-signal and large-signal performances with zero drain/source biasing condition. The proposed model demonstrates a well prediction over a wide frequency range and a wide power operating range. The input P1dB power handling capability at 2 GHz for series-type device is about the same value of 27.5 dBm from measurement and the proposed model. With driving a negative body bias, the P1dB can be improved to 30.5 dBm.