The performance improvement in SiGeSn/GeSn p-channel hetero Line Tunneling FET (HL-TFET)

In this paper, we demonstrate the performance improvement in SiGeSn/GeSn p-channel hetero line- tunneling field-effect transistor (HL-TFET) via numerical simulation. The GeSn is located at the pocket region and forms the type-II staggered tunneling junction (TJ) that perpendicular to channel direction with the lattice-matched SiGeSn. The HL-TFET demonstrates the smaller onset voltage (V-ONSET), the higher on state current (I-ON) and the steeper subthreshold swing (SS) in comparison with the GeSn homo Line TFET (L-TFET) and the conventional SiGeSniGeSn double-gate hetero-TFET (H-TFET) devices. The performance enhancement is mainly owing to the larger tunneling area in HL-TFET attributing to the presence of heterojunction and the tunneling junction (TJ) that perpendicular to the channel direction.