FPGA Implementation of A* Algorithm for Real-Time Path Planning

被引:1
|
作者
Zhou, Yuzhi [1 ]
Jin, Xi [1 ]
Wang, Tianqi [1 ]
机构
[1] Univ Sci & Technol China, Hefei, Peoples R China
关键词
Field programmable gate arrays (FPGA) - System-on-chip - Real time systems - Motion planning - Programmable logic controllers;
D O I
10.1155/2020/8896386
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The traditional A*algorithm is time-consuming due to a large number of iteration operations to calculate the evaluation function and sort the OPEN list. To achieve real-time path-planning performance, a hardware accelerator's architecture called A*accelerator has been designed and implemented in field programmable gate array (FPGA). The specially designed 8-port cache and OPEN list array are introduced to tackle the calculation bottleneck. The system-on-a-chip (SOC) design is implemented in Xilinx Kintex-7 FPGA to evaluate A*accelerator. Experiments show that the hardware accelerator achieves 37-75 times performance enhancement relative to software implementation. It is suitable for real-time path-planning applications.
引用
收藏
页数:11
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