A flexible architecture for H.263 video coding

被引：1
|
作者：
Garrido, MJ [1 ]
Sanz, C [1 ]
Jiménez, M [1 ]
Meneses, JM [1 ]
机构：
[1] Univ Politecn Madrid, E-28040 Madrid, Spain
来源：
EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, PROCEEDINGS: ARCHITECTURES, METHODS AND TOOLS | 2002年
关键词：
D O I：
10.1109/DSD.2002.1115353
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper a very flexible and efficient architecture that implements the core of a video coder according to Rec. H.263 is presented. It consists of a RISC processor that controls the scheduling of a set of specialized processors for the transforms (DCT and IDCT), quantizers (DQ and IQ), motion estimation and motion compensation (ME/MC). The architecture also includes preprocessing modules for the input video signal from the camera and interfaces for the external video memory and the H.263 bit-stream generation. The architecture has been written in synthesizable Verilog and tested using standard video sequences. It has also been prototyped into a development system based on an FPGA and a RISC.
引用
收藏
页码：70 / 77
页数：8
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