A Effective Algorithm of Hardware Synchronization on Network Processor

The performance of multithreaded network processor can be lowered when its overhead of synchronization increase. So conventional "busy-wait" synchronization algorithm restricted severely the parallel processing capability. A blocking synchronization algorithm of multithreading was proposed for the Multi-Processor System on Chip(MPSoC), which was used to actively schedule exclusive access by the synchronous arbiter on order of first in first out (FIFO). The algorithm was implemened with hardware structure which consisted of the content addressing based lock unit and synchronous request buffer. The implementation of the algorithm is able to eliminate the overhead of memory access in "busy-wait" synchronization and reduce occupancy of on-chip bus bandwidth and processores resource. Comparing with the other algorithm used in the application of packet processing, the algorithm proposed improved about 54% of the performance of the target system with reducing 29% of system power dissipation, which proved effective improvement for performance of packet processing and power dissipation.