Multi-ASIP Platform Synthesis for Real-Time Applications

被引:0
|
作者
Micconi, Laura [1 ]
Gangadharan, Deepak [1 ]
Pop, Paul [1 ]
Madsen, Jan [1 ]
机构
[1] Tech Univ Denmark, DK-2800 Lyngby, Denmark
关键词
MULTIPROCESSOR SYSTEMS; DESIGN FLOW;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper we are interested in deriving a distributed platform, composed of heterogeneous processing elements, targeted to applications that have strict timing constraints. We consider that the platform may use multiple Application Specific Instruction Set Processors (ASIPs). An ASIP is synthesized and tuned for a specific set of tasks (i.e., a task cluster). During design space exploration (DSE), we evaluate each platform solution visited in terms of its cost and performance, i.e., its ability to execute the applications such that they meet their timing constraints. To determine if the applications are schedulable, we have to know the worst-case execution time (WCET) of each task. However, we can determine the WCETs only after the ASIPs are synthesized, which is time consuming and therefore cannot be done during DSE. To address this circular dependency (the ASIPs depend on the task clustering, and the WCETs of tasks, used to determine schedulability, depend on how ASIPs are synthesized), we propose an uncertainty model for the WCETs, which captures the range of possible ASIP implementations. Based on this model, we synthesize a multi-ASIP platform, such that the applications have a high chance of being schedulable and the cost constraints imposed on the platform are fulfilled. We propose an Evolutionary Algorithm-based approach, which uses a novel stochastic schedulability analysis to solve this optimization problem. The proposed approach has been evaluated using several benchmarks.
引用
收藏
页码:59 / 67
页数:9
相关论文
共 50 条
  • [1] Dataflow-based Multi-ASIP Platform Approach for Digital Control Applications
    Frijns, R. M. W.
    Kamp, A. L. J.
    Stuijk, S.
    Voeten, J. P. M.
    Bontekoe, M.
    Gemei, K. J. A.
    Corporaal, H.
    16TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2013), 2013, : 811 - 814
  • [2] Multi-ASIP Platform Synthesis for Event-Triggered Applications with Cost/Performance Trade-offs
    Gangadharan, Deepak
    Micconi, Laura
    Pop, Paul
    Madsen, Jan
    2013 IEEE 19TH INTERNATIONAL CONFERENCE ON EMBEDDED AND REAL-TIME COMPUTING SYSTEMS AND APPLICATIONS (RTCSA), 2013, : 277 - 286
  • [3] Hierarchical DSE for multi-ASIP platforms
    Micconi, Laura
    Corvino, Rosilde
    Gangadharan, Oeepak
    Madsen, Jan
    Pop, Paul
    Jozwiak, Lech
    2013 2ND MEDITERRANEAN CONFERENCE ON EMBEDDED COMPUTING (MECO), 2013,
  • [4] System-level synthesis of multi-ASIP platforms using an uncertainty model
    Micconi, Laura
    Madsen, Jan
    Pop, Paul
    INTEGRATION-THE VLSI JOURNAL, 2015, 51 : 118 - 138
  • [5] From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding
    Muller, Olivier
    Baghdadi, Amer
    Jezequel, Michel
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2009, 17 (01) : 92 - 102
  • [6] MGP: A distributed, multi-platform, programming environment for real-time applications
    Mumolo, E
    Moratto, S
    Nolich, M
    Vercelli, G
    ITI 2001: PROCEEDINGS OF THE 23RD INTERNATIONAL CONFERENCE ON INFORMATION TECHNOLOGY INTERFACES, 2001, : 467 - 472
  • [7] A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding
    Lapotre, Vianney
    Murugappa, Purushotham
    Gogniat, Guy
    Baghdadi, Amer
    Huebner, Michael
    Diguet, Jean-Philippe
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 24 (01) : 383 - 387
  • [8] Stopping-free dynamic configuration of a multi-ASIP turbo decoder
    Lapotre, Vianney
    Murugappa, Purushotham
    Gogniat, Guy
    Baghdadi, Amer
    Huebner, Michael
    Diguet, Jean-Philippe
    16TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2013), 2013, : 155 - 162
  • [9] Protocol synthesis for real-time applications
    Khoumsi, A
    Bochmann, GV
    Dssouli, R
    FORMAL METHODS FOR PROTOCOL ENGINEERING AND DISTRIBUTED SYSTEMS, 1999, 28 : 417 - 433
  • [10] A Flexible High Throughput Multi-ASIP Architecture for LDPC and Turbo Decoding
    Murugappa, Purushotham
    Al-Khayat, Rachid
    Baghdadi, Amer
    Jezequel, Michel
    2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE), 2011, : 228 - 233