FPGA in Rough-Granular Computing: Reduct Generation

被引：11
|
作者：
Kopczynski, Maciej [1 ]
Grzes, Tomasz [1 ]
Stepaniuk, Jaroslaw [1 ]
机构：
[1] Bialystok Tech Univ, Fac Comp Sci, PL-15351 Bialystok, Poland
来源：
2014 IEEE/WIC/ACM INTERNATIONAL JOINT CONFERENCES ON WEB INTELLIGENCE (WI) AND INTELLIGENT AGENT TECHNOLOGIES (IAT), VOL 2 | 2014年
关键词：
D O I：
10.1109/WI-IAT.2014.120
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
In this paper we propose a combination of capabilities of the FPGA based device for computing reduct. Presented architecture has been tested on a real-world data. Obtained results confirm the huge acceleration of the computation time using hardware supporting reduct computation in comparison to software implementation.
引用
收藏
页码：364 / 370
页数：7
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