Using a data-flow scheme to minimize the power consumption of an embedded processor

被引：0

作者：

Chen Pinghua ^{[1
]}

Liu Yijun ^{[1
]}

Xie Guobo ^{[1
]}

Li Zhenkun ^{[1
]}

机构：

[1] Guangdong Univ Technol, Sensor Network Grp, Fac Comp, Guangzhou 510006, Peoples R China

来源：

ICCSE'2006: PROCEEDINGS OF THE FIRST INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE & EDUCATION: ADVANCED COMPUTER TECHNOLOGY, NEW EDUCATION | 2006年

关键词：

data-flow machine; low-power design; asynchronous design; computer architecture; reconfigure computing;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Data-flow processors[1][2] was a very hot research field and considered as a likely direction to "the next generation of computer" from 1970's to middle 1980's. Data-flow machines optimize their hardware for fine grain data driven parallel computation to increase the throughput. Although most attempts on data-flow machines seem unsuccessful today, we believe that data-flow architectures have power-efficiency advantage over conventional von Neumann architectures.

引用

页码：190 / 194

页数：5

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