Time-to-digital converters-A comprehensive review

被引：16

作者：

Mattada, Mahantesh P. ^{[1
,2
]}

Guhilot, Hansraj ^{[2
]}

机构：

[1] Sanjay Ghodawat Univ, Dept Elect, Kolhapur, Maharashtra, India

[2] Visvesvaraya Technol Univ, VTU Res Resource Ctr, Belagavi, India

来源：

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS | 2021年 / 49卷 / 03期

关键词：

counter TDC; delay line; flash TDC; GRO; multiphase clock; pipeline TDC; pulse shrinking; SAR TDC; time counter; time interval measurement; time-to-digital converter; Vernier delay line; Vernier ring; PHASE-LOCKED LOOP; 6; PS-RESOLUTION; CMOS TIME; INPUT-RANGE; TDC; DESIGN; FPGA; SCHEME; INTERPOLATION; CALIBRATION;

D O I：

10.1002/cta.2936

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work presents a comprehensive literature review on different topologies of time-to-digital converters (TDCs). A brief history, applications, classification, characterization, and working principle of each TDC are mentioned. A survey of both Field Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC) architectures is covered. The trade-off with respect to applications, pros, and cons of different architectures and future scope of TDC as an alternative data converter is also explored.

引用

页码：778 / 800

页数：23

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