Innovative polyimide liner deposition method for high-aspect-ratio and high-density through-silicon-vias (TSVs)

被引:15
|
作者
Ding, Yingtao [1 ]
Xiong, Miao [1 ]
Yan, Yangyang [1 ]
Wang, Shiwei [1 ]
Chen, Qianwen [1 ]
Wang, Weijing [1 ]
Chen, Zhiming [1 ]
机构
[1] Beijing Inst Technol, Sch Informat & Elect, Beijing 100081, Peoples R China
关键词
Liner; Polyimide; Through-silicon-vias (TSVs); Step coverage; POLYMER LINER; RELIABILITY; FABRICATION;
D O I
10.1016/j.mee.2015.09.009
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In three-dimensional (3D) integration, liner deposition technique with excellent step coverage is a challenge to realize through-silicon-vias (TSVs), especially for TSVs with high-aspect-ratio and high-density. This paper proposes an innovative polyimide liner deposition method, which utilizes the vacuum-assisted polymer filling and spin-coating processes, for TSV applications. The experimental SEM images and EDX analyses show that, a high-density TSV array, with a diameter of 8 mu m and depth of 60 mu m (corresponding aspect-ratio as high as 7.5:1), has been successfully deposited with uniform polyimide liner with the proposed method. Besides, the impacts of polyimide viscosity on the liner deposition characteristics have been investigated and detailed in this paper to get an optimization. The proposed polymer liner deposition approach involves simple and feasible process. It is not only versatile to polymers but also it is completely compatible to CMOS technology. It puts little limit on thermal budget of subsequent process and is valid for "via-middle" and "via-last" three-dimensional integration applications. (C) 2015 Elsevier B.V. All rights reserved.
引用
收藏
页码:78 / 84
页数:7
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