Automated Circuit Elaboration from Incomplete Architectural Descriptions

Arithmetic circuits are some of the most common circuits, yet building generators for these circuits is usually both ad-hoc and error-prone. Often, generator designers do not directly use Register Transfer Languages, but instead use scripting languages (e.g., Perl) to generate RTL and overcome the limited expressivity of typical RTL languages. We present a new approach to generator construction, where the design language is natural and expressive, and designers are provided with special facilities to alleviate typical sources of errors. This builds on previous work, where designers write an incomplete design (a sketch) and provide a functional reference; a complete, correct design is then synthesized. Notably, we address scalability problems in the general case with an approach tailored specifically for arithmetic generators: satisfying values for the uncertainties inserted in the designs are discovered incrementally as the generator parameters grow the size of the generated circuits. This approach results in significantly reduced solution times, sometimes up to 25 times faster than the nai"ve strategy.