共 50 条
- [1] NetFPGA-based Load Balancer for a Multi-Stage Router Architecture [J]. 2014 WORLD CONGRESS ON COMPUTER APPLICATIONS AND INFORMATION SYSTEMS (WCCAIS), 2014,
- [2] On-line Power Savings in a Distributed Multi-stage Router Architecture [J]. 2012 IEEE GLOBAL COMMUNICATIONS CONFERENCE (GLOBECOM), 2012,
- [3] SNMP Management in a Distributed Software Router Architecture [J]. 2011 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS (ICC), 2011,
- [4] Flow control in a multi-plane multi-stage buffered packet switch [J]. 2007 WORKSHOP ON HIGH PERFORMANCE SWITCHING AND ROUTING, 2007, : 229 - +
- [5] MBL: A Multi-Stage Bufferless High-radix Router [J]. 2016 IEEE INTERNATIONAL CONFERENCE ON CLUSTER COMPUTING (CLUSTER), 2016, : 532 - 533
- [8] MiniDeviation: An Efficient Multi-Stage Bus-Aware Global Router [J]. 2020 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2020,
- [9] Architecture for multi-stage network attack traceback [J]. LCN 2005: 30TH CONFERENCE ON LOCAL COMPUTER NETWORKS, PROCEEDINGS, 2005, : 776 - 783
- [10] Software Data Plane and Flow Switching Plane Separation in Next-Generation Router Architecture [J]. 2015 10TH INTERNATIONAL CONFERENCE ON P2P, PARALLEL, GRID, CLOUD AND INTERNET COMPUTING (3PGCIC), 2015, : 194 - 199