Electrical Performance Modeling of Unbalanced Comb Tree Networks on Advanced PCB Interconnects for High-Rate Clock Signal Distribution

Usually, the routing process is made by non-specialists in electrical simulation that only meet the requirement of the standards. The aim of this work is to supply a new tool dedicated to assess the quality of the tree network routing. An innovative modeling method of advanced unbalanced interconnections called "comb tree" for distributing high speed clock signals is featured. The flow work summarizing the routine process of new design rule is established to enhance the performance of advanced packages for high speed circuits. The analytical approach for extracting the voltage transfer function corresponding to the electrical signal paths in function of tree branch parameters is fundamentally inspired from SIMO/SISO electrical circuit analogy. Doing so, the wideband characteristic impedances and propagation constants of elementary lines constituting the tree are extracted from geometrical and physical properties. A PCB prototype of unbalanced comb tree network over FR-4 substrate has been designed and manufactured for the experimental verification. Then, frequency analyses of different VTFs have been carried out. Less than 1dB of error has been found within the DC-3GHz bandwidth and less than 4 dB within 3-10GHz. In addition, time-domain analyses with 2 Gbps input signal has been realized. Excellent agreements between transient simulations and the proposed model have been established. The model developed is potentially useful for predicting the signal integrity and optimization process of unbalanced advanced PCB and on-chip tree interconnects.