Simultaneous Switching Noise Analysis for High-Speed Interface

被引：0

作者：

Takahashi, Narimasa ^{[1
]}

Kagawa, Kenji ^{[2
]}

Honda, Yutaka ^{[2
]}

Takahashi, Yo ^{[3
]}

机构：

[1] IBM Japan Ltd, Kyoto 6048175, Japan

[2] ATE Serv, Kawasaki, Kanagawa 2130011, Japan

[3] Shibaura Inst Technol, Tokyo 1358548, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2009年 / E92C卷 / 04期

关键词：

SSN; power integrity; signal integrity; DDR;

D O I：

10.1587/transele.E92.C.460

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes the modeling and the analysis methodology to evaluate Simultaneous Switching Noise (SSN) for the combined system of the package with the 4-layer Printed Circuit Board (PCB), which the 64 Simultaneous Switching Outputs (SSOs) were included using a simple IBIS model. Simulation results showed that the ground plane in both package and PCB can be used as the reference to reduce SSN more effectively than the power plane. For the source synchronous timing technique such as used in a DDR SDRAM memory bus in the model shown in this paper, the skew control circuit tequiniqe is easy to apply in the chip design instead of using embedded capacitors in the package's substrate. And also the radiated emission and eye diagram analysis were studied.

引用

页码：460 / 467

页数：8

共 50 条

[1] Method for the analysis of simultaneous switching noise on power/ground planes in high-speed MCM
Yang, X.P.
Li, Z.F.
Cao, Y.
[J]. Shanghai Jiaotong Daxue Xuebao/Journal of Shanghai Jiaotong University, 2001, 35 (01): : 1 - 4
[2] Coupling of simultaneous switching noise to interconnecting lines in high-speed systems
Kim, J
Rotaru, MD
Chong, KC
Park, J
Iyer, MK
Kim, J
[J]. 54TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2004, : 568 - 574
[3] Complementary spiral resonators for ultrawideband suppression of simultaneous switching noise in high-speed circuits
[J]. Ghobadi, A. (amir.ghobadi.ee@gmail.com), 1600, Electromagnetics Academy (46):
[4] SIMULTANEOUS SWITCHING NOISE ENABLER IN HIGH-SPEED BIOMEDICAL SYSTEMS BY INTEGRATED PLANE COUPLING
Singh, Surender
Agarwal, Ravinder
Singh, V. R.
[J]. INSTRUMENTATION SCIENCE & TECHNOLOGY, 2015, 43 (05) : 497 - 510
[5] New simultaneous switching noise analysis and modeling for high-speed and high-density CMOS IC package design
Eo, Y
Eisenstadt, WR
Jeong, JY
Kwon, OK
[J]. IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2000, 23 (02): : 303 - 312
[6] Simultaneous Switching Noise Impact to Signal Eye Diagram on High-Speed I/O
Chan, Siang Rui
Tan, Fern Nee
Mohd-Mokhtar, Rosmiwati
[J]. 2012 4TH ASIA SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ASQED), 2012, : 200 - 205
[7] Analysis of Switching Voltage Regulator Noise Coupling to a High-Speed Signal
Joo, Junho
Singh, Soumya
Seema, P. K.
Hwang, Chulsoon
Mutnury, Bhyrav
Drewniak, James
[J]. 2022 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY & SIGNAL/POWER INTEGRITY, EMCSI, 2022, : 460 - 464
[8] Modeling of simultaneous switching noise in high speed systems
Chun, S
Swaminathan, M
Smith, LD
Srinivasan, J
Jin, Z
Iyer, MK
[J]. IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2001, 24 (02): : 132 - 142
[9] Complementary Split-Ring Resonators for Simultaneous Switching Noise Mitigation in High-Speed Circuits
Bait-Suwailam, Mohammed M.
Ramahi, Omar M.
[J]. 2010 IEEE ANTENNAS AND PROPAGATION SOCIETY INTERNATIONAL SYMPOSIUM, 2010,
[10] Minimizing Simultaneous Switching Noise at Reduced Power with Power Transmission Lines for High-Speed Signaling
Telikepalli, Satyanarayana
Swaminathan, Madhavan
Keezer, David
[J]. 2012 IEEE 21ST CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, 2012, : 29 - 32

← 1 2 3 4 5 →