New Cache Designs for Thwarting Software Cache-based Side Channel Attacks

被引:0
|
作者
Wang, Zhenghong [1 ]
Lee, Ruby B. [1 ]
机构
[1] Princeton Univ, Dept Elect Engn, PALMS, Princeton, NJ 08544 USA
关键词
Cache; Side channel; Computer architecture; Security; Processor; Timing attacks;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Software cache-based side channel attacks are a serious new class of threats for computers. Unlike physical side channel attacks that mostly target embedded cryptographic devices, cache-based side channel attacks can also undermine general purpose systems. The attacks are easy to perform, effective on most platforms, and do not require special instruments or excessive computation power. In recently demonstrated attacks on software implementations of ciphers like AES and RSA, the full key can be recovered by an unprivileged user program performing simple timing measurements based on cache misses. We first analyze these attacks, identifying cache interference as the root cause of these attacks. We identify two basic mitigation approaches: the partition-based approach eliminates cache interference whereas the randomization-based approach randomizes cache interference so that zero information can be inferred. We present new security-aware cache designs, the Partition-Locked cache (PLcache) and Random Permutation cache (RPcache), analyze and prove their security, and evaluate their performance. Our results show that our new cache designs with built-in security can defend against cache-based side channel attacks in general - rather than only specific attacks on a given cryptographic algorithm - with very little performance degradation and hardware cost.
引用
收藏
页码:494 / 505
页数:12
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