Robust Multi-VT 4T SRAM Cell in 45nm Thin BOx Fully-Depleted SOI Technology with Ground Plane

被引：2

作者：

Noel, J. -P. ^{[1
]}

Thomas, O. ^{[1
]}

Fenouillet-Beranger, C. ^{[1
]}

Jaud, M. -A. ^{[1
]}

Amara, A. ^{[2
]}

机构：

[1] CEA, LETI, MINATEC, F-38054 Grenoble, France

[2] ISEP, P-75000 Oporto, Portugal

来源：

2009 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS | 2009年

关键词：

D O I：

10.1109/ICICDT.2009.5166293

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a new compact, robust and low leakage 4T SRAM cell is proposed. It is based on an original concept Of Multi-V-T thin buried oxide (BOx) fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs with ground plane (GP) in 45nm technology node. The stability of the cell reaches 20% of V-DD and the cell leakage is 13pA. A minimum cell area of 0.209 mu m(2) with specific 45nm SRAM design rules has been reached. This is 16% smaller than the smallest 6T SRAM cell reported in 45nm Bulk technology. Moreover, the proposed cell displays a good manufacturability. It is a cost saving process because it requires only one GP doping, no substrate contact at the cell level and is based on a conventional FDSOI process flow.

引用

页码：191 / +

页数：2

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