1-level Crossing Sampling Scheme for Low Data Rate Image Sensors

A novel reading architecture for CMOS image sensor for low data rate has been investigated in this paper. The proposed architecture is designed using asynchronous logic and is intended to control and manage the flow of event-driven pixels. This architecture overcomes the standard difficulties encountered when managing simultaneous pixel requests without degrading the image sensor fill factor and resolution. Moreover, this reading architecture does not need an analog-to-digital converter and is capable of suppressing the spatial redundancies. This leads to a reduced image data flow.