EAHyper: Satisfiability, Implication, and Equivalence Checking of Hyperproperties

被引:30
|
作者
Finkbeiner, Bernd [1 ]
Hahn, Christopher [1 ]
Stenger, Marvin [1 ]
机构
[1] Saarland Univ, Saarland Informat Campus, Saarbrucken, Germany
关键词
DETERMINISM; SECURITY;
D O I
10.1007/978-3-319-63390-9_29
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
We introduce EAHyper, the first tool for the automatic checking of satisfiability, implication, and equivalence of hyperproperties. Hyperproperties are system properties that relate multiple computation traces. A typical example is an information flow policy that compares the observations made by an external observer on execution traces that result from different values of a secret variable. EAHyper analyzes hyperproperties that are specified in HyperLTL, a recently introduced extension of linear-time temporal logic (LTL). HyperLTL uses trace variables and trace quantifiers to refer to multiple execution traces simultaneously. Applications of EAHyper include the automatic detection of specifications that are inconsistent or vacuously true, as well as the comparison of multiple formalizations of the same policy, such as different notions of observational determinism.
引用
收藏
页码:564 / 570
页数:7
相关论文
共 50 条
  • [1] Combinational equivalence checking using satisfiability and recursive learning
    Marques-Silva, J
    Glass, T
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS, 1999, : 145 - 149
  • [2] An efficient sequential equivalence checking framework using Boolean Satisfiability
    Zheng, Feijun
    Weng, Yanling
    Yan, Xiaolang
    ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 1174 - 1177
  • [3] Integrating a Boolean Satisfiability Checker and BDDs for combinational equivalence checking
    Gupta, A
    Ashar, P
    ELEVENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1997, : 222 - 225
  • [4] Logic optimization and equivalence checking by implication analysis
    Kunz, W
    Stoffel, D
    Menon, PR
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1997, 16 (03) : 266 - 281
  • [5] Model Checking Quantitative Hyperproperties
    Finkbeiner, Bernd
    Hahn, Christopher
    Torfah, Hazem
    COMPUTER AIDED VERIFICATION (CAV 2018), PT I, 2018, 10981 : 144 - 163
  • [6] Model Checking Algorithms for Hyperproperties
    Finkbeiner, Bernd
    VERIFICATION, MODEL CHECKING, AND ABSTRACT INTERPRETATION, VMCAI 2021, 2021, 12597 : 3 - 16
  • [7] Statistical Model Checking for Hyperproperties
    Wang, Yu
    Nalluri, Siddhartha
    Bonakdarpour, Borzoo
    Pajic, Miroslav
    2021 IEEE 34TH COMPUTER SECURITY FOUNDATIONS SYMPOSIUM (CSF 2021), 2021, : 1 - 16
  • [8] Combinational equivalence checking using Boolean Satisfiability and Binary Decision Diagrams
    Reda, S
    Salem, A
    DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS, 2001, : 122 - 126
  • [9] Satisfiability checking for logic with equality and uninterpreted functions under equivalence constraints
    Kozawa, Hiroaki
    Hamaguchi, Kiyoharu
    Kashiwabara, Toshinobu
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2007, E90A (12) : 2778 - 2789
  • [10] BOOLEAN SATISFIABILITY AND EQUIVALENCE CHECKING USING GENERAL BINARY DECISION DIAGRAMS
    ASHAR, P
    GHOSH, A
    DEVADAS, S
    INTEGRATION-THE VLSI JOURNAL, 1992, 13 (01) : 1 - 16