Predicting thermomechanical stress using mesmeric methodology

Packaged IC's are subjected to thermomechanical stress during manufacture and operation. Accurate characterisation of these stresses, which may induce failure, is complex and is the subject of the work in this paper. This paper firstly describes a methodology for predicting thermomechanical stress in packaged die. A novel test chip with piezoresistive strain gauges is designed to allow detailed mapping of the stress distribution on the die surface. Two measurement techniques were developed for characterisation of the strain gauges. A vacuum test fixture allows characterisation of the gauges at wafer level and a four point bending fixture was developed for measurement of wafer strips. 3D finite element techniques were used to simulate the stresses on the samples in the measurement fixtures. Simulated stresses were used in conjunction with resistance changes measured in the fixtures to calculate the piezoresistive coefficients for the strain gauges. Secondly, this paper investigates one of the most commonly used assumptions in finite element modelling of encapsulation induced stresses, namely that all package materials are stress free at encapsulation temperature. Simulated results are compared with measured package warpage and the results indicate that package warpage may be overpredicted using this assumption.